The present invention relates to a packet switch applied to a cross-connect switch, a router, etc. and serving to forward (including transmitting and transferring as far as it is not particularly specified) fixed-length packets (cells), and more particularly to an input buffer type and input/output buffer type switch as one mode of a large-scale packet switch architecture.
With an explosive spread of the Internet and an advent of media dealing with large-capacity high-quality data over the recent years, more expectations have been given to a construction of an infra-structure for a large-scale communications network capable of flexibly dealing with the large-capacity data. Then, much attention is focused on a broadband switch having a switching capacity on the order of several hundreds of Giga-bytes to several Tera-bytes as a key for actualizing the network on that scale.
Of the packet switches, applied to those switches, for forwarding the fixed-length packets, the basic input buffer type switch (see FIG. 1) including a single FIFO type input buffer memory provided for every incoming route (input line (highway): HW), has a problem of HOL (Head Of Line) blocking, and it is known that a throughput is limited to 58.6% at the maximum. What is known as a method of avoiding this HOL blocking is to logically segmenting each input buffer memory of the input buffer unit into queues corresponding to the outgoing routes (output lines), and execute scheduling of a forwarding right in accordance with a predetermined algorithm (see FIG. 2).
Based on this method, an operation speed of the input buffer unit is decreased, and a large-capacity buffer unit using a general-purpose memory can be constructed. Further, a core switch serving as a common switch unit is bufferless and is therefore capable of minimizing the hardware, while a scheduler is capable of reducing the operation speed with a dispersion pipeline architecture (see FIG. 3).
Herein, the input buffer memory is shared between the logic outgoing queues, and hence it is required that an address used per queue be managed. If the input buffer memory comes to a large capacity, however, an address management memory (FIFO) also increases in capacity (see FIG. 4). An address link mode using pointers is, it has hitherto been known, used for reducing the capacity of the address management memory (see FIG. 5).
The general-purpose memory for configuring the input buffer unit may be classified into an SRAM that is comparatively small in capacity but is random-accessible at a high speed, and a DRAM that is large in capacity but requires a burst access in order to access at a high speed. In the case of increasing a capacity of a packet (cell) buffer memory by use of DRAM, a contrivance is that the burst access can be attained within a range of a packet length (see FIG. 6).
Further, a common device takes a dual architecture as a redundant architecture, wherein a cross-connection is provided for every block, and switching is effected through a selector. A reliability of the device is thereby enhanced (see FIG. 7). In the input buffer unit, a reading process is executed at the same speed with all package cards.
Further, as the services have been diversified, the interfaces corresponding to a wide range of speeds from a high speed down to a low speed have been provided. It is desired that the interfaces corresponding to the different line speeds be accommodated in mixture at a high efficiency in the common router and in the cross-connect switch.
According to conventional methods of accommodating those interfaces in mixture, the interfaces are accommodated in mixture in a way of multiplexing a plurality of low-speed lines and increasing port speeds of the router and of the cross-connect switch, or in a way of changing the speed with the buffer memory provided in the line interface. The former method, however, needs a packet multiplexer (MUX) for performing high-speed multiplexing in a temporary manner even when accommodating a comparatively small number of line interfaces. Further, according to the latter method, the low-speed interface available at a relatively low price requires a high-speed buffer memory.
The memory address management needs the address management memories corresponding to the buffer memory capacity even when using the address link mode. By contrast, there is a method of utilizing a part of buffer memory area as an address management memory. According to this method, however, the number of accesses to the packet buffer memory increases, which might become a bottle neck to high-speed accessing (see FIG. 8).
Moreover, in the case of actualizing a multicast function, the same packet buffer memory is used in a plurality of logic outgoing route queues, and therefore the address link is unable to be configured, with the result that the address link mode can not be applied (see FIG. 9).
The packet buffer memories are, if having a scheme to use the memories at a speed as high as possible, required to be set in parallel. A parallelism for processing the packets is, however, restricted by a packet length. For instance, it is 53 bytes in ATM (Asynchronous Transfer Mode). In that case, if processed in all-bit parallel, it follows that all pieces of data are read by one single access. Thus, when increasing the parallelism, the burst access in the case of using the DRAM can not be applied, and this makes the high-speed access impossible (see FIG. 10).
The dual architecture is taken as the redundant architecture of the input buffer unit, and hence both of a hardware quantity and the number of inter-block connections are doubled, resulting in an increase in costs. Herein, it might be considered that an N+1 redundant architecture is adopted for decreasing the costs, however, the common switches (core switches) disposed at the rear stage of the input buffer unit may be conceived as one cluster on the whole. It is therefore difficult to apply this redundant architecture.
Further, when the schedulers are disposed in dispersion in the respective input buffer units, transmission routes for the scheduling data are connected in ring, and hence, if one piece of package card is removed from between the input buffer units, the data transmission is inevitably cut (see FIG. 11).